Cache invalidation sequence system utilizing odd and even invali

Details Cache invalidation sequence system utilizing odd and even invali Cache invalidation sequence system utilizing odd and even invali

1996-02-15

1997-01-28

Swann, Tod R.

Boots, shoes, and leggings

395405, 395427, 395454, 364DIG1, G06F 1200, G06F 1206

Patent

active

055985513

ABSTRACT:
By expanding the cache address invalidation queue into bit slices for holding odd invalidation addresses and even invalidation addresses and also by providing a more efficient series of transition cycles to accomplish cache address invalidations both during a cache hit or a cache miss cycle, the present architecture and methodology permits a faster cycle of cache address invalidations when required and also permits a higher frequency of processor access to cache without the processor being completely locked out from cache memory access during heavy traffic and high level of cache invalidation conditions.

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