Boots – shoes – and leggings
Patent
1983-09-22
1987-03-03
Williams, Archie E.
Boots, shoes, and leggings
G06F 1300, G06F 1314
Patent
active
046480307
ABSTRACT:
One of a plurality of devices on a common communications path (68) has a local memory (54) that is accessible by other devices on the common communications path (68). Another device on the common communications path (68) may include a cache memory (190) that keeps copies of certain of the data contained by the local memory (54). If another device on the common communications path (68) accesses the local memory (54), the cache (190) is kept apprised of this fact by monitoring of the common communications path (68), and it sets an internal flag to indicate that the data involved may not be valid. However, the contents of memory 54 may also be accessed by means of a processor (50) without using the common communications path (68). Accordingly, provisions are made to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the common communications path ( 68). In this way, non-path accesses of a local memory can be permitted, yet proper invalidation of cache memories can be performed in a simple manner.
REFERENCES:
patent: 3735360 (1973-05-01), Anderson et al.
patent: 4228503 (1980-10-01), Waite et al.
patent: 4410944 (1983-10-01), Kronies
patent: 4445174 (1984-04-01), Fletcher
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4503497 (1985-03-01), Krygowski et al.
patent: 4503501 (1985-03-01), Coulson et al.
patent: 4513367 (1985-04-01), Chan et al.
"A Systematic Approach to the Design of Digital Bussing Structures" by Kenneth J. Thurber et al., Fall Joint Computer Conference, 1972, pp. 719-740.
Bhandarkar Dileep P.
Bomba Frank C.
Grady, III J. J.
Lackey, Jr. Stanley A.
Mitchell Jeffrey W.
Digital Equipment Corporation
Williams Archie E.
LandOfFree
Cache invalidation mechanism for multiprocessor systems does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache invalidation mechanism for multiprocessor systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache invalidation mechanism for multiprocessor systems will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1020951