Cache including decoupling register circuits

Details Cache including decoupling register circuits Cache including decoupling register circuits

1991-04-01

1996-01-30

Gossage, Glenn

395458, 395470, 395476, 395250, G06F 1300, G06F 1328

Patent

active

054887097

ABSTRACT:
A memory cache apparatus compatible with a wide variety of bus transfer types including non-burst and burst transfers. The memory cache apparatus includes a random access memory, a host port, and a system port. The memory cache apparatus further includes an input register connected to the host port for selectively writing data to the random access memory and an output register connected to the system port for receiving data from the random access memory and selectively furnishing the data to the host port or the system port. In one embodiment, the input register is a memory write register, and the output register includes a read hold register and a write back register. A cache memory system decouples a main memory subsystem from a host data bus so as to accommodate parallel cache-hit and system memory transfer operations for increased system speed and to hide system memory write-back cycles from a microprocessor. Differences in the speed of the local and system buses are accommodated, and an easy migration path from non-burst mode microprocessor based systems to burst mode microprocessor based systems is provided. Various memory organizations are accommodated including direct-mapped or one-way set associative, two-way set associative, and four-way set associative.

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Intel Corporation, "i486 Microprocessor Hardware Manual", 1990, pp. 6-1 to 6-39.

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