Cache hierarchy design for use in a memory management unit

Details Cache hierarchy design for use in a memory management unit Cache hierarchy design for use in a memory management unit

1987-06-26

1991-01-15

Clark, David L.

Boots, shoes, and leggings

G06F 1210

Patent

active

049858297

ABSTRACT:
A cache hierarchy to be managed by a memory management unit (MMU) combines the advantages of logical and virtual address caches by providing a cache hierarchy having a logical address cache backed up by a virtual address cache to achieve the performance advantage of a large logical address cache, and the flexibility and efficient use of cache capacity of a large virtual address cache. A physically small logical address cache is combined with a large virtual address cache. The provision of a logical address cache enables reference count management to be done completely by the controller of the virtual address cache and the memory management processor in the MMU. Since the controller of the logical address cache is not involved in the overhead associated with reference counting, higher performance is accomplished as the CPU-MMU interface is released as soon as the access to the logical address cache is completed.

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Fletcher, R. P. and Martin, D. B., "Store Buffer", IBM Technical Disclosure Bulletin, vol. 25, No. 9, pp. 4522-4526.

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