Cache flash controlling method for cache memory system

Details Cache flash controlling method for cache memory system Cache flash controlling method for cache memory system

1995-07-27

1997-11-25

Chan, Eddie P.

395470, G06F 1208

Patent

active

056921500

ABSTRACT:
A cache flash controlling method for a cache memory system of the write back type wherein the time required for discrimination of a dirty line in a flash cycle is reduced and system performances are improved. In the cache controlling method, all lines having tag addresses of a cache memory are divided into a plurality of blocks, and for each of the blocks, a dirty detection bit indicating whether or not a dirty line is present in the block is prepared. For those of the blocks whose data line detection bit indicates presence of no dirty line, lines of the block are invalidated immediately without performing a discrimination operation of a dirty line.

REFERENCES:
patent: 5155824 (1992-10-01), Edenfield et al.
patent: 5452249 (1995-09-01), Miyamoto et al.
patent: 5539894 (1996-07-01), Webber

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