Cache/disk subsystem with load equalization

Details Cache/disk subsystem with load equalization Cache/disk subsystem with load equalization

1980-11-14

1983-11-15

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

044159706

ABSTRACT:
In a system wherein processors are connected through channel units to disk devices, two storage control units (SCU's) are provided between the channel units and the disk devices. The SCU's receive commands from the processor and issue seek instructions to the devices to locate the disk space specified by the commands, provided that a copy of the data from the specified disk space is not resident in a cache store. The commands may be queued for a time in a memory which is accessible by both SCU's. Before issuing a seek instruction to a device, an SCU first determines whether it is the only SCU having a path through a channel unit back to the processor which issued the command or whether there is a path from each SCU to the processor. If both SCU's have a path back to the processor, the SCU issues an untagged seek instruction to the device. If not, the SCU issues a tagged seek instruction to the device. When the disk device completes a seek resulting from a tagged instruction, it sends an interrupt to the SCU which issued the seek and that SCU then notifies the processor which issued the command. In response to the notification the processor issues the command a second time and it is then executed under the control of the SCU. When a device completes a seek resulting from an untagged seek instruction it sends an interrupt to both SCU's and either one may respond to it.

REFERENCES:
patent: 3449722 (1969-06-01), Tucker
patent: 3725864 (1973-04-01), Clark et al.
patent: 4207609 (1980-06-01), Luiz et al.

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