Cache device for supplying a fixed word length of a variable ins

Details Cache device for supplying a fixed word length of a variable ins Cache device for supplying a fixed word length of a variable ins

1993-06-21

1994-04-05

Dixon, Joseph L.

Boots, shoes, and leggings

3642613, 364260, 364938, 3649483, 364DIG1, 395375, G06F 1200

Patent

active

053012895

ABSTRACT:
An instruction fetching device includes one or both of a cache device and a branch history table. The cache device stores a plurality of pairs, each pair including an instruction string divided into minimum unit instructions and an address of the instruction string. At the time of reading an instruction, an instruction string is selected and output by every minimum unit instruction from at least two pairs. The branch history table stores a plurality of pairs, each pair including a branch destination address and a set of an address of a branch instruction and a value obtained by subtracting a given value from the address. At the time of reading an instruction, first, a pair having an address of a branch instruction which address is the nearest to a head address of an instruction string to be read out is selected from a plurality of pairs, each pair including an address of a branch instruction which address is in a predetermined address range including the instruction string to be read out, or each pair of the plurality of pairs including a value obtained by subtracting a given value from the address of the branch instruction. Then, a branch destination address is selected and output from the pair which is selected first from the plurality of pairs.

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K. G. Tan, "Cache Organization with Various Line Sizes" IBM Tech. Disclosure Bulletin, vol. 25, No. 3A, pp. 1282-1284, Aug. 1982.
"Next-Sequential Prefetching Using a Branch History Table," IBM Tech. Disclosure Bulletin, vol. 29, No. 10, pp. 4502-4503, Mar. 1987.

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