Cache controller index address generator

Details Cache controller index address generator Cache controller index address generator

1994-07-06

1996-09-10

Eng, David Y.

Boots, shoes, and leggings

3649642, 3642434, G06F 1300

Patent

active

055553796

ABSTRACT:
The invention is a device for determining an address of a modified line in a cache memory and retrieving a tag, a data, and a corresponding associativity to execute a copyback routine to an external memory for the modified line. The cache memory includes an attribute array, a tag array, and a data array. The device includes a priority lookahead encoder logic circuit which simultaneously checks a status bit in each line of the attribute array to determine whether one or more modified lines are indicated. The priority lookahead encoder logic circuit then prioritizes the modified lines, if more than one is detected, for purposes of a copyback routine writing the modified lines to external memory. The device then generates an address of external memory which corresponds to each of the modified lines as and when each becomes next in priority for copyback. Finally, the device retrieves and holds data which corresponds to each of the modified lines for copyback.

REFERENCES:
patent: 4141067 (1979-02-01), McLagan
patent: 4394732 (1983-07-01), Swenson
patent: 4463420 (1984-07-01), Fletcher
patent: 4953079 (1990-08-01), Ward et al.
patent: 5140690 (1992-08-01), Hata et al.
patent: 5224217 (1993-06-01), Zangenehpour
patent: 5394531 (1995-02-01), Smith

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