Patent
1994-11-30
1997-01-28
Elmore, Reba I.
395427, 395458, 395478, G06F 13362
Patent
active
055985505
ABSTRACT:
In a multi-processing system (10), a cache controller is implemented to efficiently process collisions which occur when a predetermined address location in a data memory (26) is simultaneously accessed by two processors (20, 21). The cache controller is formed by both a cache control logic circuit (34) and a tag unit (36). In the tag unit (36), a snoop tag cache (40) and a data tag cache (42) respectively indicate whether a snooped value or an accessed data value is stored in data memory (26). A status bit array (41) provides status information for both tag caches (40, 42). By configuring the array (41) to store status information for both snoop and data tag caches (40, 42), status information is "forwarded" between tag caches (40, 42) when a collision occurs. Additionally, the cache controller modifies the timing of each of the accesses such that the status information may be "forwarded" more easily. The timing modification is also referred to as "resource pipelining."
REFERENCES:
patent: 4322795 (1982-03-01), Lange et al.
patent: 4345309 (1982-08-01), Arulpragasam et al.
patent: 4392200 (1983-07-01), Arulpragasam et al.
patent: 4620275 (1986-10-01), Wallach et al.
patent: 4646233 (1987-02-01), Weatherford et al.
patent: 4731739 (1988-03-01), Woffinden et al.
patent: 4926317 (1990-05-01), Wallach et al.
patent: 4992930 (1991-02-01), Gilfeather et al.
patent: 5056002 (1991-10-01), Watanabe
patent: 5168560 (1992-12-01), Robinson et al.
patent: 5193163 (1993-03-01), Sanders et al.
patent: 5228135 (1993-07-01), Ikumi
patent: 5247649 (1993-09-01), Bandoh
patent: 5251310 (1993-10-01), Smelser et al.
patent: 5276828 (1994-01-01), Dion
patent: 5276835 (1994-01-01), Mohan et al.
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5307477 (1994-04-01), Taylor et al.
patent: 5335335 (1994-08-01), Jackson et al.
patent: 5339399 (1994-08-01), Lee et al.
patent: 5515518 (1996-05-01), Stiles et al.
"An On-Chip 72K Pseudo Two-Port Cache Memory Subsystem" by S. C-M. Chuang et al. and published in 1990 Symposium on VLSI Circuits: Digest of Technical Papers, Jun. 7-9, 1990.
"Multiprocessor Cache Synchronization-Issues, Innovations, Evolution" written by Philip Bitar a Alvin M. Despain and published in IEEE Transactions on Computers in 1986, pp. 424 to 433.
"Efficient Synchronization Primitives For Large-Scale Cache-Coherent Multiprocessors" writter J. Goodman, M. Vernon, and P. Woest; published in the ASPLOS-III Proceedings in 1989, pp. 64-75.
Golab James S.
Moyer William C.
Shen Gene W.
Elmore Reba I.
Motorola Inc.
Witek Keith E.
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