Cache control which inhibits snoop cycles if processor accessing

Details Cache control which inhibits snoop cycles if processor accessing Cache control which inhibits snoop cycles if processor accessing

1995-04-18

1996-12-10

Black, Thomas G.

Boots, shoes, and leggings

36424341, 36424344, 3642463, 364DIG1, 395479, 395480, 395466, G06F 1200, G06F 1300

Patent

active

055840175

ABSTRACT:
A multi-processor cache control system wherein cache control information is encoded into the address bits of a memory access request. The encoded cache control information is used to optimize cache control functions. Each memory access request is comprised of at least two elements. First, an address field is provided to define the location of the desired data item. Secondly, cache control information is provided in a cache control field within each memory access request. The cache control field comprises a plurality of bits that define a relationship between the address field and a plurality of local caches associated with processors in a multi-processor system. This relationship determines which of a plurality of local caches may cache the data item referenced by the address within the address field.

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