Cache control for use in a multiprocessor to prevent data from p

Details Cache control for use in a multiprocessor to prevent data from p Cache control for use in a multiprocessor to prevent data from p

1995-05-18

1998-01-27

Chan, Eddie P.

395451, 395448, G06F 1208

Patent

active

057130043

ABSTRACT:
A multiprocessor cache control uses ping-pong bits to reduces the number of invalidate cycles on a shared system bus in a multiprocessor system with a plurality of caches when data is being updated by multiple CPUs. The ping-pong bit is used predict when sharing is taking place and convert read-shared requests into read-exclusive requests.

REFERENCES:
patent: 5317716 (1994-05-01), Liu

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