Cache control circuit in cache memory unit with unit for enablin

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Details

364900, 3649642, 3642434, 36424341, G06F 1300

Patent

active

049549448

ABSTRACT:
A cache control circuit in a cache memory unit having a cache memory in cooperation with an address conversion unit for converting a logical address into a physical address, a main memory, and a central processing unit. The central processing unit issues a control signal comprising a write/read request together with a logical address. The address conversion unit converts the logical address into the physical address which is applied to the cache memory unit. When the address conversion unit does not have a physical address corresponding to the logical address, the address conversion unit delivers a mismatch signal to the central processing unit and the cache control circuit to inform them of invalidation of the issued read/write request. The cache memory unit decides whether or not the physical address received is valid in the cache memory unit and produces a hit signal when it is valid. When the control signal has a read request as the read/write request, the cache control circuit produces a read access signal for carrying out the read operation prior to decision of the hit signal and the mismatch signal. Accordingly, the read access time to the cache memory is reduced. When the control signal has a write request as the read/write request, the cache control circuit produces a write access signal for writing data from the central processing unit into the cache memory after the decision of the hit signal and the non-mismatch signal is performed.

REFERENCES:
patent: 4197580 (1980-04-01), Chang et al.
patent: 4398243 (1983-08-01), Holberger et al.
patent: 4453230 (1984-06-01), Mizoguchi et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4646233 (1987-02-01), Weatherford et al.

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