Boots – shoes – and leggings
Patent
1994-12-23
1996-06-25
Ray, Gopal C.
Boots, shoes, and leggings
395468, 395473, 364243, 36424341, 3642731, 3642733, 364240, 364DIG1, G06F 132
Patent
active
055309321
ABSTRACT:
A multiprocessing system maintains cache coherency during a reduced power mode of operation. The multiprocessing system has a first and a second processor coupled to the bus to perform data transactions with the main memory. During the reduced power mode of operation, the internal clock signal of the second processor is decoupled from a portion of the internal logic of the second processor while remaining coupled to a portion of the internal logic of the second processor that is used to monitor and respond to the traffic on the external bus to maintain cache coherency. During the reduced power mode of operation, the second processor continues to perform snoop and write-back processes to maintain a cache coherent multiprocessing system.
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Carmean Douglas M.
Crawford John
Intel Corporation
Ray Gopal C.
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