Cache coherent computer system that minimizes invalidation and c

Details Cache coherent computer system that minimizes invalidation and c Cache coherent computer system that minimizes invalidation and c

1997-05-12

1998-01-06

Swann, Tod R.

395472, 395473, 395470, 395471, G06F 1208

Patent

active

057064636

ABSTRACT:
A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor. Such data include read-only code segments. The code segments, including instructions and data, are shared among the multiple processors. The requesting processor generates a Read to Share Always request upon a cache miss of a read-only datablock, and generates a Read to Share request otherwise. The Read to Share Always request results in the datablock stored in cache memory being labeled as in a "shared" state, while the Read to Share request results in the datablock being labeled as in an "exclusive" state.

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