Cache coherency method and apparatus for a multiple path interco

Details Cache coherency method and apparatus for a multiple path interco Cache coherency method and apparatus for a multiple path interco

1990-12-24

1993-09-28

Dixon, Joseph L.

Boots, shoes, and leggings

395325, 364DIG1, 3642402, 3642434, 36424341, 36424344, 364964, 36496431, G07F 1200, G07F 1300

Patent

active

052492834

ABSTRACT:
A method and apparatus for providing coherency for cache data in a multiple processor system with the processors distributed among multiple independent data paths. The apparatus includes a set of cache monitors, sometimes called snoopers, associated with each cache memory. There are the same number of monitors as there are independent data paths. Thus, each cache stores cache tags that correspond to its currently encached data into each of the monitors of the set associated therewith. Thus, each cache has an monitor associated therewith which monitors each of the multiple paths for an operation at an address that corresponds to data stored in its cache. If such an access is detected by one of the set of monitors, the monitor notifies its cache so that appropriate action will be taken to ensure cache data coherency.

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