Cache coherency mechanism for multiprocessor computer systems

Details Cache coherency mechanism for multiprocessor computer systems Cache coherency mechanism for multiprocessor computer systems

1995-05-10

1998-02-10

Lane, Jack A.

395471, 395473, G06F 1200

Patent

active

057178984

ABSTRACT:
A multiprocessor computer system which maintains cache coherency includes first and second microprocessors each having an associated cache memory storing lines of data. Each line of data has associated protocol bits that indicate a protocol state consistent with write-through, write-back, or write-once cache coherency policies that are selected via a protocol selection terminal for different system configurations. In one configuration, the output and external address terminals of the first microprocessor are coupled to the external and output address terminals, respectively, of the second microprocessor. This configuration enables each microprocessor to snoop memory cycles to main memory initiated by the other microprocessor so that it can be readily determined if a particular cache has the latest version of data.

REFERENCES:
patent: 3723976 (1973-03-01), Alvarez et al.
patent: 4484267 (1984-11-01), Fletcher
patent: 4612612 (1986-09-01), Woffinden et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 4785398 (1988-11-01), Joyce et al.
patent: 4847804 (1989-07-01), Shaffer et al.
patent: 4939641 (1990-07-01), Schwartz et al.
patent: 4991081 (1991-02-01), Bosshart
patent: 5008813 (1991-04-01), Crane et al.
patent: 5025366 (1991-06-01), Baror
patent: 5113510 (1992-05-01), Hillis
patent: 5140681 (1992-08-01), Uchiyama et al.
patent: 5146603 (1992-09-01), Frost et al.
patent: 5148533 (1992-09-01), Joyce et al.
patent: 5179675 (1993-01-01), Cole et al.
patent: 5301298 (1994-04-01), Kagan et al.
patent: 5367660 (1994-11-01), Gat et al.
patent: 5379396 (1995-01-01), Gochman et al.
Sweazey et al., Cache Memory Requirements in RISC Computers, Electro/87 and Mini/Micro Northeast Conference Record, Dec. 3, 1987, pp. 1-6, Los Angeles, CA USA.

Affiliated with

Also associated with

Rating

Cache coherency mechanism for multiprocessor computer systems does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache coherency mechanism for multiprocessor computer systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache coherency mechanism for multiprocessor computer systems will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2086347