Cache coherency maintenance of non-cache supporting buses

Details Cache coherency maintenance of non-cache supporting buses Cache coherency maintenance of non-cache supporting buses

1995-01-17

1997-10-14

Chan, Eddie P.

395465, 395466, 395842, 395843, G06F 1208, G06F 1316

Patent

active

056780257

ABSTRACT:
A cache coherency apparatus for computer systems not having a cache supporting bus is described. The cache coherency apparatus monitors the communication on a bus between a CPU and an external device connected to the bus. The cache coherency apparatus monitors the bus in order to determine when the external device is being programmed by the CPU for a memory modification of a main memory also coupled to the bus. Upon determining that the external device is being programmed for a modification of main memory, the cache coherency apparatus generates cache control signals to a cache memory. Using these cache control signals, the cache coherency apparatus causes the contents of the cache memory to be flushed prior to the memory access performed by the external device. In addition, the cache coherency apparatus generates other cache control signals to disable the locations of main memory being modified from being transferred into the cache memory while the memory access by the external device is taking place. Once the memory access being performed by the external device is complete, the cache coherency apparatus generates additional cache control signals to again enable the caching of previously disabled portions of the main memory. In this manner, the coherency of the cache memory may be maintained even though two or more memory access devices (i.e., a CPU and external devices) both modify locations within the main memory.

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