Cache coherency in a multiprocessing system

Details Cache coherency in a multiprocessing system Cache coherency in a multiprocessing system

1994-10-03

1997-08-19

Chan, Eddie P.

G06F 1208

Patent

active

056597088

ABSTRACT:
A multiprocessor system utilizing a plurality of bus devices coupled via a shared bus utilizes a specially coded signal to notify a bus device initiating a read or a read with intent to modify operation that the requested data, or cache line, is in a modified state within a cache of another bus device. Unlike the modified response signal, this special signal is sent along with the requested data from the one bus device to the requesting bus device, indicating that this data has priority over any data being sent from the memory system coupled to the shared bus. The present invention allows for cache-to-cache and cache-to-memory-and-cache operations.

REFERENCES:
patent: 5301281 (1994-04-01), Kennedy
patent: 5388224 (1995-02-01), Maskas
patent: 5504874 (1996-04-01), Galles et al.
Handy, "The Cache Memory Book", 1993, pp. 152-157.

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