Cache cell with masking

Static information storage and retrieval – Associative memories – Ferroelectric cell

Reexamination Certificate

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Details

C365S154000, C365S156000, C711S108000

Reexamination Certificate

active

06995997

ABSTRACT:
A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor; a comparison cell, including third and fourth transistors controlling a fifth transistor, connected in series with a sixth inhibiting transistor to a result line; and a second storage cell, including a seventh transistor in series with two inverters in anti-parallel and an eighth transistor, the second storage cell controlling the inhibiting transistor. The first, second, seventh, and eighth transistors may be N-channel transistors, and the third, fourth, fifth, and sixth transistors may be P-channel transistors.

REFERENCES:
patent: 5422838 (1995-06-01), Lin
patent: 5642114 (1997-06-01), Komoto et al.
patent: 6044005 (2000-03-01), Gibson et al.
patent: 6295576 (2001-09-01), Ogura et al.
patent: 6341079 (2002-01-01), Chadwick
patent: 6480931 (2002-11-01), Buti et al.
patent: 198 39 205 (1999-03-01), None
Preliminary French Search Report from French Patent Application No. 00/11242, filed Sep. 4, 2000.
European Search Report from related European Patent Application No. 01 41 0110.
Patent Abstracts of Japan, vol. 1996, No. 05, May 31, 1996 & JP 08 007580 A (Hitachi Ltd.) Jan. 12, 1996.
Patent Abstracts of Japan, vol. 013, No. 537, Nov. 30, 1989 & JP 01 220293 A (NEC Corp) Sep. 1, 19896.

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