Cache bypass system with post-block transfer directory examinati

Details Cache bypass system with post-block transfer directory examinati Cache bypass system with post-block transfer directory examinati

1981-10-15

1985-02-19

Thomas, James D.

Boots, shoes, and leggings

G06F 906, G06F 1300

Patent

active

045009546

ABSTRACT:
A storage hierarchy has a caching buffer and a backing store; the backing store preferably having disk-type data-storage apparatus. A directory indicates data stored in the caching buffer. Upon a data-storage access, read or write, within a series of such accesses, resulting in a cache miss, all subsequent data storage accesses in the series are made to the backing store to the exclusion of the caching buffer even though the caching buffer has storage space allocated for such a data transfer. Selected limits are placed on the series to the backing store, such as receiving on end of series (end of command chain) indication from a using unit, crossing DASD cylinder boundaries, receiving an out of bounds address or receiving certain device oriented commands.

REFERENCES:
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patent: 4394733 (1983-07-01), Swenson
patent: 4398243 (1983-08-01), Holberger et al.
patent: 4407016 (1983-09-01), Bayliss et al.
patent: 4429363 (1984-01-01), Duke et al.
patent: 4430701 (1984-02-01), Christian et al.
patent: 4445176 (1984-04-01), Burk et al.
patent: 4445177 (1984-04-01), Bratt et al.
patent: 4466059 (1984-08-01), Bastian et al.
IBM System/360 and System/370 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information, IBM Publication GA 22-6974-4, pp. 7-8, 13-14, 19-24, Fifth Edition (1978).

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