Cache bypass control for operand fetches

Details Cache bypass control for operand fetches Cache bypass control for operand fetches

1978-03-16

1980-02-19

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 100

Patent

active

041897706

ABSTRACT:
In the case of a cache miss, the successive fetch requests by the I-unit for sublines (e.g. doublewords) of a variable length field operand are provided by the first through the highest-address fetched sublines in a line being accessed from main storage via a cache bypass. This avoids the time delay for the I-unit caused by waiting until the complete line has been transferred to the cache before all required sublines in the line are obtainable from the cache. Address operand pairs (AOP's) consisting of request and buffer registers are provided in the I-unit to handle the fetched sublines as fast as the cache bypass can provide them from main storage. If there is a cache hit, the sublines are accessed from the cache.

REFERENCES:
patent: 3496550 (1970-02-01), Schachner
patent: 3569938 (1971-03-01), Eden et al.
patent: 3588829 (1971-06-01), Boland et al.
patent: 3806888 (1974-04-01), Brickman et al.
patent: 3896419 (1975-06-01), Lange et al.

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