Cache bus snoop protocol for optimized multiprocessor computer s

Details Cache bus snoop protocol for optimized multiprocessor computer s Cache bus snoop protocol for optimized multiprocessor computer s

1995-04-21

1997-12-30

Robertson, David L.

395496, 395287, G06F 1200, G06F 1338

Patent

active

057040583

ABSTRACT:
A cache bus snoop protocol optimizes performance of a multiprocessor computer system with multiple level two caches by allocating windows of cache bus snoop activity on a need basis. When a cycle to cacheable address space is requested, the cache bus is granted only after the necessary snoop and write-back cycles are completed. During the snoop and write-back cycles, snoop activity by other devices in inhibited.

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