Cache burst architecture for parallel processing, such as for im

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395164, G06F 1500

Patent

active

055577342

ABSTRACT:
A parallel processing system for processing data matrices, such as images, is disclosed. The system includes a plurality of processing units, organized in four blocks of eight processing units per processing chip, and external cache burst memory, wherein each processing unit is associated with at least one column of the external memory. A barrel shifter connected between the memory and the processing units allows data to be shifted to adjacent processing chips, thus providing the means for connecting several of the chips into a ring structure. Further, digital delay lines are connected between the barrel shifter and the processing units, thus providing the capability of delaying, via a predetermined number of clock cycles, incoming column data. Each processing unit is provided with a nine bit cache memory. The system further includes a controller for each chip that sequences a burst of consecutive rows of a data matrix from the external cache burst memory, to be stored in either the cache memory associated with each of the processing units or routed directly to the processors included in each processing unit.
The barrel shifters and the delay lines cooperate to bring horizontally and vertically displaced data points in the external memory to a single processing unit in a single clock cycle period. The controller decodes instructions stored in the external memory, wherein each processing unit receives the same instruction at any given cycle; this decoded instruction is valid for subsequent data bursts from external memory, thus providing the means for allowing instructions and data to be stored in the same external memory without a significant performance penalty. Where the width of an image is greater than the number of processing units, the image must be segmented to be stored in memory. An efficient method of relating column data across segment boundaries is thus provided, using the cache memory of selected processing units.

REFERENCES:
patent: 3537074 (1970-10-01), Stokes et al.
patent: 3582899 (1971-06-01), Semmelhaack
patent: 3970993 (1976-07-01), Finnila
patent: 4174514 (1979-11-01), Sternberg
patent: 4215401 (1980-07-01), Holsztynski et al.
patent: 4314349 (1982-02-01), Batcher
patent: 4484346 (1984-11-01), Sternberg et al.
patent: 4524455 (1985-06-01), Holstynski
patent: 4525797 (1985-06-01), Holden
patent: 4541116 (1985-09-01), Lougheed
patent: 4546428 (1985-10-01), Morton
patent: 4550437 (1985-10-01), Kobayashi et al.
patent: 4580215 (1986-04-01), Morton
patent: 4612628 (1986-09-01), Beauchamp et al.
patent: 4621339 (1986-11-01), Wagner et al.
patent: 4635292 (1987-01-01), Mori et al.
patent: 4665556 (1987-05-01), Fukushima et al.
patent: 4685144 (1987-08-01), McCubbrey et al.
patent: 4731724 (1988-03-01), Michel et al.
patent: 4736288 (1988-04-01), Shintani et al.
patent: 4739474 (1988-04-01), Holsztynski et al.
patent: 4742552 (1988-05-01), Andrews
patent: 4763294 (1988-08-01), Fong
patent: 4780842 (1988-10-01), Morton et al.
patent: 4787057 (1988-11-01), Hammond
patent: 4829585 (1989-05-01), Pape
patent: 4858163 (1989-08-01), Boreland
patent: 4866651 (1989-09-01), Bleher et al.
patent: 4872133 (1989-10-01), Leeland
patent: 5129092 (1992-07-01), Wilson
patent: 5268856 (1993-12-01), Wilson
patent: 5410649 (1995-04-01), Gove
patent: 5428804 (1995-06-01), Davies
patent: 5450603 (1995-09-01), Davies
Fisher, A. L., "Scan Line Array Processors for Image Computation", Jun. 1986, pp. 338-345 IEEE Conference Proceedings, 13th Annual Int'l Symposium on Computer Architecture.
Budzinski, et al., "A Restructruable Integrated Circuit for Implementing Programmable Digital Systems" Mar. 1982, pp. 43-54, Computer, vol. 15, No. 3.
Kondo, et al., "An LSI Adaptive Array Processor," Apr. 1993, pp. 147-156, IEEE Journal of Solid-State Circuits, vol. SC-18, No. 2.
Graham, et al., "Parallel Algorithms and Architectures for Optical State Estimation," Nov. 1985, pp. 1061-1068, IEEE Transactions on Computers, vol. 34, No. 1.
O'Leary, D. P., "Systolic Arrays for Matrix Transpose and Other Reorderings," Jan. 1987, pp. 117-122, IEEE Transactions on Computers, vol. C-36, No. 1.
Fountain, T. J., "A Survey of Bit-Serial Array Processor Circuits," 1983, pp. 1-14, Computing Structures for Image Processing.
Danielsson, P. E., "LIPP--Proposals for the Design of and Image Processor Array," 1983, pp. 157-178, Computing Structures for Image Processing.
Ralston, et al., Encyclopedia of Computer Science and Engineering, pp. 14-15 and 714 (2nd Ed. 1983).
Wilson, S. S., "The Pixie-5000--A Systolic Array Processor," (1985), pp. 477-483 (1985) Workshop on Computer Architecture for Pattern Analysis and Image Data Base Management.
Strong, J. P. "Basic Imaging Processing Algorithms on the Massively Parallel Processor," (1982), pp. 48-52, Multicomputers and Image Processing.
A. L. Fisher, et al., "Architecture of VLSI SIMD Processing Element, " Oct. 1987, pp. 324-327, IEEE International Conference on Computer Design: VLSI in Computers.
A. L. Fisher and P. Highnam, "Real-Time Image Processing on Scan Line Array Processors," Nov. 1985, pp. 484-489, IEEE Workshop on Pattern Analysis and Image Data Base Management.
"Computing Speeds Soar with Parallel Processing," Jun. 1988, pp. 49-58, Computer Design "Parallel-Processing Concepts Finally Come Together in Real Systems," Jun. 1987, pp. 51-74 Computer Design.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Cache burst architecture for parallel processing, such as for im does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache burst architecture for parallel processing, such as for im, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache burst architecture for parallel processing, such as for im will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-421086

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.