Cache block replacement scheme based on directory control bit se

Details Cache block replacement scheme based on directory control bit se Cache block replacement scheme based on directory control bit se

1993-05-24

1996-07-09

Kim, Matthew M.

Boots, shoes, and leggings

364DIG1, 3642281, 36424341, 364246, 395447, 395448, 395485, 395460, G06F 1208

Patent

active

055353614

ABSTRACT:
A cache controller for a multithreading multiprocessor system which starts an execution of another thread by suspending an ongoing execution of a thread when a cache miss happens. The cache controller comprises a cache directory unit for storing cache managing data including a footprint bit to indicate a mapping relation between at least one cache block in a main memory block, an access control unit for searching the directory unit based on an access requesting message inputted thereto through its input/output port connected to a processor to return one of a cache hit notice and a cache miss notice, as well as transferring messages with the main memory through its input/output port connected to a network, and a footprint bit changing device for setting the footprint bit in the cache managing data corresponding to a cache block at a cache hit, while resetting the footprint bit upon input of a positive responding message through the input/output port connected to the network to a fetch requesting message which has been sent therethrough at a cache miss.

REFERENCES:
patent: 4484267 (1984-11-01), Fletcher
patent: 4807110 (1989-02-01), Pomerene et al.
patent: 4843542 (1989-06-01), Dashiell et al.
patent: 4882642 (1989-11-01), Tayler et al.
patent: 4885680 (1989-12-01), Anthony et al.
patent: 4928225 (1990-05-01), McCarthy et al.
patent: 5179702 (1993-01-01), Spix et al.
patent: 5185875 (1993-02-01), Chinnaswamy et al.
patent: 5297269 (1994-05-01), Donaldson et al.
patent: 5313609 (1994-05-01), Baylor et al.
patent: 5430850 (1995-07-01), Papadopoulos et al.
Kurihara, K., "Latency tolerance through multi-threading in large-scale multiprocessors" (Proceedings of the International Symposium on Shared Memory Multiprocessing 7, pp. 91-101, Publication Date 1991.
Vuong-Adlerberg, I., "Cache for Multi-Threaded Processors on a Split-Transaction Bus" (MIT Cambridge Lab. for Computer Science, Report No.:MIT/LCS/TR-466), Nov. 1989.
"April: A Processor Architecture for Multiprocessing", in Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 104-114, 1990 Agarwal, Lim, Kranz, Kubitatowiz.
Lenonski, Lavdon, Gharachorloo, Gupta, Hennessy "The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor", 1990, pp. 148-159.
"Synchronization, Coherence, and Event Ordering in Multiprocessors", 1988, pp. 9-21 Dubois and Schevrich.

Affiliated with

Also associated with

Rating

Cache block replacement scheme based on directory control bit se does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache block replacement scheme based on directory control bit se, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache block replacement scheme based on directory control bit se will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1875965