Cache arrangement for direct memory access block transfer

Details Cache arrangement for direct memory access block transfer Cache arrangement for direct memory access block transfer

1982-03-25

1985-03-12

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 900, G06F 1300, G06F 938

Patent

active

045049025

ABSTRACT:
A cache memory system reduces cache interference during direct memory access block write operations to main memory. A control memory within cache contains in a single location validity bits for each word in a memory block. In response to the first word transferred at the beginning of a direct memory access block write operation to main memory, all validity bits for the block are reset in a single cache cycle. Cache is thereafter free to be read by the central processor during the time that the remaining words of the block are written without the need for additional cache invalidation memory cycles.

REFERENCES:
patent: 4056844 (1977-11-01), Izumi
patent: 4197580 (1980-04-01), Chang et al.
patent: 4268907 (1981-05-01), Porter et al.
patent: 4398243 (1983-08-01), Holberger et al.
patent: 4403288 (1983-09-01), Christian et al.

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