Cache address strobe control logic for stimulated bus cycle init

Details Cache address strobe control logic for stimulated bus cycle init Cache address strobe control logic for stimulated bus cycle init

1995-06-20

1996-03-12

Chan, Eddie P.

Boots, shoes, and leggings

395403, 395464, 395494, 395500, 364DIG1, 3642391, 3642384, 3642423, 36424341, 3642514, 3642618, G06F 1202

Patent

active

054993539

ABSTRACT:
A cache control system generates an alternate cache control signal to unload a CPU driven bus control signal without interfering with the bus control of the other processors in the system. The alternate cache control signal removes most of the loading from the control signals of the CPU. One feature of the cache control system enables an increase in the external cache capacity of the computer system by increasing the number of synchronous SRAM chips which can be controlled by the system. Another feature enables an increase in the system performance time for memory accesses from the external cache by decreasing delays in the receipt of cache control signals.

REFERENCES:
patent: 4912632 (1990-03-01), Gach et al.
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patent: 5339399 (1994-08-01), Lee et al.
patent: 5450565 (1995-09-01), Nadir et al.
Klanseck, R. M., "Interface speeds bus data swaps," EDN Electrical Design News, vol. 27, No. 5, pp. 160 and 163, Mar. 1992.
Legenhausen, J., et al., "Second-Level Cache for the 80486 Using a PLD-Based Cache Controller," Wescon Conference Record, vol. 36, pp. 76-83, Nov. 1992.

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