Cache address modification control

Details Cache address modification control Cache address modification control

1994-12-16

1997-10-14

Swann, Tod R.

395445, G06F 1202

Patent

active

056780184

ABSTRACT:
A cache memory is provided which adjusts its response to addresses in accordance with the number of identical cache memory cards installed in the motherboard. Upon its installation in the motherboard a card is informed of its status as a master or a slave. As long as a slave is not installed the master responds to processor accesses over the entire address range of the computer. When a slave is installed a signal is sent to the master. Circuitry on the memory cards restricts the master response to half the address range. The slave being informed of its status restricts its response to the other half of the address range.

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IBM Technical Disclosure Bulletin, vol. 36, No. 12, Dec. 1993, pp. 613-616, "Method of Accessing Uniquely Identically Addressed Input/Output Ports", E. Schorn.
IBM Technical Disclosure Bulletin, vol. 35, No. 1A, Jun. 1992, pp. 375-376, "Dynamically Resizing The Cache Control Table to Improve Working Set", Cox et al.

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