Railway switches and signals – Miscellaneous – Signals and indicators
Reexamination Certificate
2008-06-02
2010-12-14
Le, Mark T (Department: 3617)
Railway switches and signals
Miscellaneous
Signals and indicators
C246S16700M, C714S010000, C714S011000, C714S012000
Reexamination Certificate
active
07850127
ABSTRACT:
A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function.
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Berecek Sean P.
Ding Zhu
Lemonovich John E.
Sharp William A.
Werner James C.
Ansaldo STS USA, Inc.
Eckert Seamans Cherin & Mellott , LLC
Houser, Esq. Kirk D.
Le Mark T
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