C-MOS thin film transistor device manufacturing method

Fishing – trapping – and vermin destroying

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437 29, 437 57, 437913, 148DIG150, 148DIG137, H01L 21265

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053169603

ABSTRACT:
A method for manufacturing a C-MOS thin film transistor device has the steps of implanting the n-type impurity only in the upper layer portion of the source-drain section of the n-channel transistor by controlling implantation energy of the n-type impurity; implanting the p-type impurity in the source-drain section and the gate electrode of the p-channel transistor, and the source-drain section and the gate electrode of the n-channel transistor by controlling implantation energy of the p-type impurity; and activating the implanted n-type and p-type impurities in the source-drain section of the n-channel transistor, and activating the implanted p-type impurity in the source-drain section and the gate electrode of the p-channel transistor and gate electrode of the n-channel transistor. The n-type and the p-type may be respectively changed to the p-type and the n-type in the above construction.

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Ipri et al, "Low-threshold Low-Power CMOS/SOS for High Frequency Counter Applications", IEEE Journal of solid-state circuits, vol. SC-11, No. 2, Apr. 1976, pp. 329-336.

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