C-MOS logic circuit supplied with narrow width pulses converted

Details C-MOS logic circuit supplied with narrow width pulses converted C-MOS logic circuit supplied with narrow width pulses converted

1985-01-23

1987-06-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307452, 307481, 307240, 307265, 307266, 307267, H03K 1716, H03K 19003, H03K 19096

Patent

active

046706720

ABSTRACT:
A logic circuit comprises an input terminal receiving an input signal of input pulses; first and second stages of C-MOS circuit formed by a first MOS FET of one channel type formed in said semiconductor substrate of one conductivity type and a second MOS FET of other channel type formed in well region of other conductivity type formed in the semiconductor substrate, said first and second stages being connected in a cascade connection; a first power terminal applying a first power voltage to the semiconductor substrate; a second power terminal applying a second power voltage to the well region; and a pulse converter converting the input signal to a pulse signal having a reference voltage of the second power voltage and short width pulses of the first power voltage produced in synchronism with the input pulses.

REFERENCES:
patent: 3862440 (1975-01-01), Suzuki et al.
patent: 3867648 (1975-02-01), Christenson
patent: 3937982 (1976-02-01), Nakajima
patent: 4047057 (1977-09-01), Ahmed
patent: 4370569 (1983-01-01), Hunsinger

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