1985-11-19
1988-06-07
James, Andrew J.
357 41, 357 45, 357 71, H01L 2702
Patent
active
047500263
ABSTRACT:
In a C MOS IC as shown in FIG. 7(A) and FIG. 8, the IC comprises vertical row of horizontally long blocks, each block comprising p-type MOS transistor region and n-type MOS transistor region, the IC comprises horizontal wirings of aluminum (31, 32, 33) and vertical wirings of polycrystalline silicon (61, 62, 63, 64, 65, 41, 42), with insulation films on the upper side and on the lower side of the polycrystalline silicon film, between the rows (I, II, . . .), said horizontal aluminum wirings (31, 32, 33) and said polycrystalline silicon wiring (61, 62 . . ., 41, 42) being appropriately connected through openings (105, 105 . . .) formed in said insulation film inbetween, said vertical polycrystalline silicon wirings being connected through aluminum wirings in said blocks.
REFERENCES:
patent: 4053336 (1977-10-01), Grundy et al.
patent: 4412237 (1983-10-01), Matsumura et al.
patent: 4481524 (1984-11-01), Tsujide
patent: 4549198 (1985-10-01), Kondo
Ichinohe Eisuke
Kuninobu Shigeo
Crane Sara W.
James Andrew J.
Matsushita Electric - Industrial Co., Ltd.
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