C-MOS arithmetic - logic unit with high carry propogation speed

Details C-MOS arithmetic - logic unit with high carry propogation speed C-MOS arithmetic - logic unit with high carry propogation speed

1988-04-27

1989-10-10

Harkcom, Gary V.

Boots, shoes, and leggings

364768, G06F 750

Patent

active

048736597

ABSTRACT:
The arithmetic-logic unit has elementary cells performing logic addition, one for each pair of operand bits, which are particularly optimized as far as carry propogation speed is concerned and are controlled by an auxiliary fast logic allowing their performance to be extended to the other operations. The unit also has a control signal generating circuit, subdivided into a first part (DEC1), near the elementary cell of least significant position, which generates an operation selecting signal for all the cells, and into a second part (DEC2), near the elementary cell of most significant position, which generates control signals for the auxiliary logic of each elementary cell.

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Steinlechner et al., "Carry-Save Adders and Their Application for a Multiplication with Factored Multiplicands", Proceedings IEEE International Conference on Computer Design: VLSI in Computers, New York, Oct. 7-10, 1985, pp. 359-362.

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