Byte wide EEPROM with individual write circuits and write preven

Details Byte wide EEPROM with individual write circuits and write preven Byte wide EEPROM with individual write circuits and write preven

1984-03-01

1986-07-08

Moffitt, James W.

Static information storage and retrieval

Floating gate

Particular biasing

365189, 365195, G11C 700, G11C 1140

Patent

active

045997071

ABSTRACT:
An array arrangement for EEPROMS in which each memory cell has two transistors. Selection is simplified whereby in selecting a cell all of the cells in the selected row are connected to one terminal of the writing circuit and all the cells in the selected column are connected to the other terminal. This selection process prevents any cell from being written into except the cell at the intersection of the selected row and the selected column.

REFERENCES:
patent: 4090258 (1978-05-01), Cricchi
patent: 4149270 (1979-04-01), Cricchi et al.
patent: 4477884 (1984-10-01), Iwahashi et al.

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