Byte-wide dynamic RAM with multiplexed internal buses

Details Byte-wide dynamic RAM with multiplexed internal buses Byte-wide dynamic RAM with multiplexed internal buses

1982-04-29

1984-05-15

Fears, Terrell W.

Static information storage and retrieval

Addressing

365189, 365233, G11C 1300

Patent

active

044492073

ABSTRACT:
An MOS dynamic RAM organized in a byte-wide arrangement is described. An internal bus is used for multiplexed column address signals and data. Other multiplexing reduced the lines associated with the input/output circuits. A unique power-on circuit automatically resets clock generators if they are not operative after power is applied.

REFERENCES:
patent: 3402398 (1968-09-01), Koerner et al.

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