Byte tracking system and method

Details Byte tracking system and method Byte tracking system and method

1992-03-27

1994-03-08

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 851, H04J 300

Patent

active

052933814

ABSTRACT:
A byte tracking system (60) has a 32-bit wide system data bus (34). System bus interface unit (48) connects the system bus (34) to the transmit FIFO buffer memory (42) to supply 4-byte data words (62) to the FIFO buffer memory (42). The FIFO buffer memory (42) has word write and read accessibility. A 4:1 multiplexer (64) is connected at the output side of the FIFO buffer memory (42) by a 32-bit wide bus (66). The multiplexer (64) is used to multiplex correct bytes (63) from the data words (62) to an 8-bit output bus (68). A byte tracker circuit (70) controls the multiplexer (64) and determines which byte (63) is to be sent to the output bus (68). The bytes (63) supplied to output bus (68) are converted by a parallel to serial converter (69) to a serial bit stream, which is supplied to Manchester encoder/decoder (36).

REFERENCES:
patent: 3988545 (1976-10-01), Kuemmerle et al.
patent: 4309765 (1982-01-01), Mueller et al.
patent: 4974225 (1990-11-01), Chenier et al.
patent: 5014272 (1991-05-01), Yoshida
patent: 5020055 (1991-05-01), May, Jr.

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