Byte synchronization system and method using an error correcting

Details Byte synchronization system and method using an error correcting Byte synchronization system and method using an error correcting

1997-07-08

2000-07-18

Chung, Phung M.

Excavating

371 437, 371 436, 371 46, G06F 1100, H04L 1200

Patent

active

06089749&

ABSTRACT:
A byte synchronization detection system and method in which a vector subtractor circuit determines an error vector between a current read data pattern and a synchronization bit pattern, and an offset adder circuit determines a Hamming Distance of the next read data pattern by adding the difference between the Hamming Distance from current error vector to the synchronization bit pattern and the Hamming Distance from the next error vector to the synchronization bit pattern. The Hamming Distance is determined by selected elements of the error vector which are the output from the vector subtractor circuit. The offset adder circuit determines a difference between the Hamming Distance of the current read data pattern and of the next read data pattern. The synchronization bit pattern is between 16 and 18 bits in length, inclusive. This approach reduces the probability of synchronization failure and/or mis-synchronization about 4 orders of magnitude over conventional approaches, while also reducing the length of the byte synchronization pattern to 16 bits.

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