Byte-swap hardware simulator for a sixteen bit microprocessor co

Details Byte-swap hardware simulator for a sixteen bit microprocessor co Byte-swap hardware simulator for a sixteen bit microprocessor co

1992-05-29

1994-08-02

Lall, Parshotam S.

Boots, shoes, and leggings

395325, 3642403, 3642549, 3642551, G06F 1300

Patent

active

053353404

ABSTRACT:
An arrangement for enabling a sixteen bit microprocessor to transfer data to and from a peripheral unit operating in an eight bit mode includes a single OR gate for simulating an odd address so that only the low byte portion of the data bus is utilized. A subroutine in the microprocessor causes the microprocessor to act as if all addresses in the peripheral unit are even and to force the OR gate to an active state whenever the real address in the peripheral unit is odd.

REFERENCES:
patent: 4374416 (1983-02-01), Catiller et al.
patent: 4447878 (1984-05-01), Kinnie et al.
patent: 4716527 (1987-12-01), Graciotti
patent: 4831514 (1989-05-01), Turlakov et al.
patent: 5243701 (1993-09-01), Muramatsu et al.
"i486 Microprocessor Hardware Reference Manual" pp. 7-3-7-8, 1990 Intel. Corp.
"MC68030 User's Manual" pp. 7-5 to 7-11 1989, Motorola Inc.

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