Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-11-08
2004-02-24
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185290
Reexamination Certificate
active
06697281
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
NOT APPLICABLE
STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
NOT APPLICABLE
REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK.
NOT APPLICABLE
BACKGROUND OF THE INVENTION
The present invention relates to flash electrically-erasable, programmable read-only memories (EEPROMs). In particular, the present invention relates to flash EEPROMs having selectable groups.
FIG. 1A
is a cross-sectional view of a standard floating gate tunnel oxide (FLOTOX) cell
20
. In the FLOTOX cell
20
, there is a polysilicon control gate
22
where a control voltage V
CG
may be applied, a polysilicon floating gate
24
, a source terminal having a source voltage potential V
S
coupled to an n-type region
32
, a drain terminal having a drain voltage potential V
D
, and another polysilicon
26
over two n-type regions,
28
and
30
, forming a select transistor on a p-type substrate
34
. An inter-poly dielectric region
38
is defined between the two polysilicon pieces
22
and
24
(control gate and floating gate); two gate-dielectric regions
40
and
44
are defined by the respective polysilicon areas; and a tunnel dielectric region is defined by the tunnel window region
36
of the polysilicon piece
24
(floating gate). Due to the specific shape of the control gate
22
and the floating gate
24
, a tunnel window region
36
is defined to allow the tunneling of electrons.
FIG. 1B
is a schematic representation of the FLOTOX cell
20
, in which a FLOTOX transistor
46
is coupled in series with a select transistor
48
. In operation, the select transistor
48
is turned on in order to operate the FLOTOX transistor
46
. A drain/source terminal
50
serves as the source terminal for the select transistor
48
and the drain terminal for the FLOTOX transistor
46
.
Programming of the FLOTOX memory cell is carried out by applying a relatively high voltage pulse between the control gate
22
and the drain terminal
30
when there is a positive voltage applied at the select gate terminal
26
. The high voltage pulse initiates carrier generation in the substrate and causes electrons to penetrate the tunnel-dielectric region
42
and accumulate in the floating gate
24
. In a likewise manner, in erasing the memory cell, an inverse voltage is applied between the gate and drain terminals. Thus, the negative electrons in the floating gate are drawn to the drain through the thin tunnel oxide.
The erase and program operations are achieved by taking advantage of the Fowler-Nordheim (F-N) tunneling mechanism occurring between the floating gate
24
and the silicon substrate
34
through a thin oxide called the tunnel oxide
42
. A tunnel window
36
defines the area of the tunnel oxide where a large tunnel window would improve the speed of the erase/program operation but would also increase the cell size. A thinner tunnel oxide region
42
would reduce the tunneling voltage requirement and reduce the erase/program operation time. However, such a memory cell is more difficult to manufacture and may have increased reliability concerns.
Thus, attributes of the FLOTOX cell
20
include a relatively long tunneling time, a relatively large tunneling voltage, and a relatively long erase time.
FIG. 2A
is a cross-sectional view of another important type of non-volatile memory, the flash memory. In the flash memory cell
60
, there is a drain (
62
or
64
) and a source (
64
or
62
) region deposited on and within a substrate
76
. Over the substrate and the drain and source regions, insulating layers
66
and
68
are deposited. Over the insulating layers, a floating gate
70
is disposed in such a manner to partially overlap one of the drain and source regions. A second insulating layer
72
is then deposited over the floating gate
70
. A control gate
74
is then disposed over the floating gate
70
and partially overlapping the other region.
FIG. 2B
is the schematic representation of the memory cell
60
showing its circuit symbol.
In operation, the flash memory cell
60
is erased when the drain and source terminals are connected to ground and a high voltage is applied at the control gate
74
, causing electrons in the floating gate
70
to tunnel to the control gate
74
. Comparing the tunneling process occurring in the FLOTOX memory cell
20
of
FIG. 1A
, the tunneling of electrons in the flash memory cell
60
of
FIG. 2A
is a faster process requiring lower voltage potential across the respective terminals. Additionally, the typical erase time for the flash memory cell is less than 1 ms with approximately 14 volts applied. The erase time and/or (lower) voltage potential can be further improved by modifying and optimizing the dimensions of the memory cell.
To program the memory cell, the control gate
74
is set to be barely-on (around 2 volts), the terminal connected to the region
62
, away from the floating gate
74
, is connected to ground, and the terminal connected to the region
64
closer to the floating gate
74
is provided with a high voltage, generally around 12 volts. In this manner, an electric field is generated in the direction of the region
62
away from the floating gate
70
, causing electrons to travel through the channel region and be injected into the floating gate
70
, thereby charging the gate and programming the memory cell
60
. The flow of the electrons in this process is called hot carrier injection and is illustrated by the arrows.
FIG. 3A
shows a memory array
80
having a plurality of interconnected flash memory cells
60
arranged in rows and columns. The flash memory cells
60
are connected in such a manner that the terminals closer to the floating gates
70
are designated as the source terminals. The control gates
74
of the memory cells along the same row are connected to the same word line (e.g., WL
0
, WL
1
, etc.). The word lines are controlled and operated by a row address decoder
82
in response to a given row address. The source terminals of the memory cells along the same row are connected to the same source line (e.g. SL
0
, SL
1
, etc.). The source lines are also controlled and operated by the row address decoder
82
. In a similar manner, the drain terminals of the memory cells along the same columns are connected to the same bit line (e.g., BL
0
, BL
1
, etc.). The bit lines are controlled and operated by a column decoder
84
in response to a given column address (Y-MUX is a column address line multiplexer). In a read operation, the signals are amplified by a sense amplifier
86
and put into an output buffer
88
. In a program operation, data is first stored in an input buffer
90
before it is passed through the column decoder
84
for storage. In order to properly program data into the memory cells, data stored in the memory cells on the same row will have to be erased before the program operation. The reason here is that the control gate of the memory cells on the same row are connected to the same word line and hence will be affected as a group. In comparison, in such a memory array using flash memory cells, the memory cells have to be altered on a large block basis (here the entire row) while a memory array using FLOTOX memory cells can be altered on a byte to byte basis. When a memory array is altered on a block basis, invariably some of the data that does not need to be altered has to be rewritten back into the memory array which consumes time and power in the process.
FIG. 3B
is similar to
FIG. 3A
except that the flash memory cells
60
are connected in such a manner that the terminals farthest from the floating gates
70
are designated as the source terminals. The consequences of this difference are detailed below.
The row address decoder
82
and column address decoder
84
control the bit lines, word lines and source lines during erase, program and read operations as detailed in Tables 1A and 1B. Table 1 A gives the operating characteristics for the memory cell of
FIG. 2
using the flash memo
Ho Hoai
Townsend and Townsend / and Crew LLP
Winbond Electronics Corporation
LandOfFree
Byte-selectable EEPROM array utilizing single split-gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Byte-selectable EEPROM array utilizing single split-gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Byte-selectable EEPROM array utilizing single split-gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3334614