Byte-programmable flash memory having counters and secondary sto

Details Byte-programmable flash memory having counters and secondary sto Byte-programmable flash memory having counters and secondary sto

1998-08-10

1999-12-21

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518508, 36518528, 36518529, G11C 1604

Patent

active

060058102

ABSTRACT:
A byte-programmable/byte-erasable flash memory system having on-chip counters and secondary storage for word line and bit line disturbance control during program and erase operations. The counters count the numbers of program/erase cycles and compare them with empirically pre-determined counter limits; when the program/erase count exceeds the counter limit, the data then carried in the system are temporarily transferred onto the secondary storage while the memory array is refreshed and the counters are reset. The lifetime of the resulting flash memory system is improved because of decreased erase and program stresses in the memory array.

REFERENCES:
patent: 5485595 (1996-01-01), Assar et al.
patent: 5491657 (1996-02-01), Haddad et al.
patent: 5708605 (1998-01-01), Sato

Affiliated with

Also associated with

Rating

Byte-programmable flash memory having counters and secondary sto does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Byte-programmable flash memory having counters and secondary sto, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Byte-programmable flash memory having counters and secondary sto will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-511786