Byte error rate test arrangement

Details Byte error rate test arrangement Byte error rate test arrangement

1993-01-28

1996-01-09

Beausoliel, Jr., Robert W.

Excavating

375276, 379 83, 379 84, G06F 1100

Patent

active

054835429

ABSTRACT:
An arrangement is disclosed for determining a byte error rate (ByER) of a received digital signal. In particular, a local byte clock signal is generated and a complement of the received signal (or clock signal) is compared to the clock signal (or received signal). When both are the same logic value, as determined by a series of logic gates, an error is deemed to have occurred. A counter is utilized to track a number of occurrences N over a predetermined period of time T. The byte error rate is then determined from the relation ##EQU1##

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"2.4 Gb/s Sonet Multiplexer/Demultiplexer with Frame Detection Capability", IEEE Journal on Selected Areas In Communications, vol. 9, No. 5, Jun. 1991 Dennis T. Kong.

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