Byte erasable EEPROM fully compatible with a single power supply

Details Byte erasable EEPROM fully compatible with a single power supply Byte erasable EEPROM fully compatible with a single power supply

1995-09-25

1997-03-18

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518518, 36518533, G11C 700

Patent

active

056129130

ABSTRACT:
A byte erasable memory with an EEPROM type functionality that can be integrated in a fully compatible way with a standard FLASH process is composed by a matrix of FLASH cells organized in n bytes, each of m bits, addressable through a plurality of wordlines and bitlines. The EEPROM-type memory has an auxiliary selection structure composed of an n number of byte select transistors, a plurality of individually selectable source biasing lines and a plurality of select lines in the same number of the wordlines and selectable in a biunivocal way with the wordlines. The cells of a byte have a common source that is accessed and individually selectable through the respective select transistor. EEPROM functionality is obtained without any modification of the standard FLASH fabrication process by splitting the voltage applied between a control gate and the respective common source region of the cells that compose a certain selected byte about a common ground potential, during a byte erasing phase thus reducing the electrical stress induced on deselected cells.

REFERENCES:
patent: 4949309 (1990-08-01), Rao
patent: 5033023 (1991-07-01), Hsia et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5270980 (1993-12-01), Pathak et al.
patent: 5319604 (1994-06-01), Imondi et al.
patent: 5339279 (1994-08-01), Toms et al.
patent: 5430674 (1995-07-01), Javanifard

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