Patent
1996-06-10
1999-11-30
Teska, Kevin J.
395898, G06F 9135
Patent
active
059957468
ABSTRACT:
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.
REFERENCES:
patent: 4739470 (1988-04-01), Wada et al.
patent: 4823201 (1989-04-01), Simon et al.
patent: 4896133 (1990-01-01), Methvin et al.
patent: 4967343 (1990-10-01), Ngai et al.
patent: 5073864 (1991-12-01), Methvin
patent: 5222225 (1993-06-01), Groves
patent: 5467473 (1995-11-01), Kahle et al.
Complaint filed by Digital Equipment Corporation against Intel Corporation, in U.S. District Court for the District of Massachusetts, May 12, 1997.
Answer To complaint filed by Intel Corporation in U.S. District Court for the District of Massachusetts, Jul. 2, 1997.
Amended Answer to complaint and counter claim, filed by Intel Corporation in U.S. District Court for the District of Massachusetts, Aug. 12, 1997.
Intel Product Specification, "i860.TM. 64-Bit Microprocessor," Intel Corporation, Santa Clara, CA., Oct. 1989, pp. 5-1 to 5-72.
Kane, "MIPS R200 RISC Architecture," Prentice Hall, Englewood Cliffs, NJ., 1987, pp. 1-1 to 4-11 and pp. A-1 to A-9, A-64 to A-67.
Radin, "The 801 Minicomputer," IBM Research Report, IBM Corporation, Yorktown Heights, NY, Nov. 11, 1981, pp. 1-23.
Patterson et al., "Computer Architecture: A Quantitative Approach," Appendix E, "Survey of RISC Architectures," pp. E-1 to E-24, Morgan Kaufmann Pub. Inc., San Mateo, CA., 1990.
"Two-step digit comparator pares hardware," Electronic Design, vol. 31, No. 22, Oct. 1983, Denville, New Jersey, pp. 242, 244.
Sites Richard Lee
Witek Richard T.
Digital Equipment Corporation
Mohamed Ayni
Teska Kevin J.
LandOfFree
Byte-compare operation for high-performance processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Byte-compare operation for high-performance processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Byte-compare operation for high-performance processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1685051