Communications: electrical – Digital comparator systems
Patent
1974-12-16
1976-08-31
Shaw, Gareth D.
Communications: electrical
Digital comparator systems
G06F 1300
Patent
active
039784568
ABSTRACT:
A microprogrammed processor which receives 16-bit words as input data from an I/O system, breaks down each received word into four 4-bit bytes, and performs all logical and arithmetic operations on a byte-by-byte basis. The processed bytes may either be stored for further use or reconstituted into 16-bit words and outputted to the I/O system. The processor includes two source buses for applying information to an arithmetic unit (AMU), a destination bus for receiving the AMU output, as well as circuits such as memories and registers for selectively applying AMU input information to the source buses and for receiving AMU output information from the destination bus. Certain ones of the memories can both apply information to source buses and receive information from the destination bus on the same machine operation. Microprogrammed controlled gating facilities specify the circuits that are to be connected to the buses on each machine operation.
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R. Gruner et al., "Standard LSI Chips Breed a Fast New Series of Minicomputers" in Electronics, Nov. 9, 1970, pp. 64-69.
Bell Telephone Laboratories Incorporated
Chapnick Melvin B.
Duft D. M.
Shaw Gareth D.
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