Byte alignment for serial data receiver

Details Byte alignment for serial data receiver Byte alignment for serial data receiver

2005-11-29

2005-11-29

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Parallel to serial

C341S100000

Reexamination Certificate

active

06970117

ABSTRACT:
A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

REFERENCES:
patent: 5689195 (1997-11-01), Cliff et al.
patent: 6724328 (2004-04-01), Lui et al.
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2002/0190751 (2002-12-01), Lee et al.
patent: 2003/0052709 (2003-03-01), Venkata et al.

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