Byte aligner and frame synchronizer for 622 MBIT/S high-speed da

Details Byte aligner and frame synchronizer for 622 MBIT/S high-speed da Byte aligner and frame synchronizer for 622 MBIT/S high-speed da

1996-09-16

1999-01-19

Pham, Chi H.

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

370512, 370513, 370514, 375365, 375366, 375368, H04L 708

Patent

active

058621431

ABSTRACT:
A byte aligner and frame synchronizer for 622 Mbit/s high speed data includes a clock divider, a data width extension circuit, a byte alignment controller, a byte alignment circuit, a pattern selector, a continuous pattern detector, a frame pulse generator, a frame sync detector, a frame sync loss detector, and frame sync error detector, and performs byte alignment very fast while also stabilizing frame synchronization by reinforcing an error correction function.

REFERENCES:
patent: 4748623 (1988-05-01), Fujimoto
patent: 5710774 (1998-01-01), Suh et al.
IEEE Communications Magazine, Feb. 1990 .Choi, DooWhan;`Frame Alignment in a Digital Carrier System-A Tutorial`pp. 47-54.
"ICC 75" Xiaokang, Lin et al `A New Desing of the STM-1 Frame Aligner`pp. 1-4.

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