Bypassable adder

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Details

C708S670000

Reexamination Certificate

active

09938978

ABSTRACT:
An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the second input (B), the logic circuit configured to hold at least one of the first input (A) and the second input (B) according to the bypass input (bypass).

REFERENCES:
patent: 3482085 (1969-12-01), Smith, Jr.
patent: 4746899 (1988-05-01), Swanson et al.
patent: 4751666 (1988-06-01), Gillingham
patent: 5333288 (1994-07-01), Kusuda
patent: 5875124 (1999-02-01), Takahashi
patent: 5953241 (1999-09-01), Hansen et al.
patent: 6308190 (2001-10-01), Willson, Jr. et al.
Chevillat, Pierre R. et al., “Optimum FIR Transmitter and Receiver Filters for Data Transmission over Band-Limited Channels,” IEEE Transactions on Communications, vol. Com-30, No. 8, Aug. 1982, pp. 1909-1915.
Kuo, Tzu-Chieh et al., “A Programmable Interpolation Filter for Digital Communications Applications,” Proceedings of the 1998 IEEE Interpolation Symposium on Circuits and Systems, May 31-Jun. 3, 1998, Monterey, CA, IEEE, 1998, vol. II, pp. II-98-II-100.
Kuo, Tzu-Chieh, “A Programmable Interpolation Filter for Digital Communication Applications,” Thesis, Master of Science in Electrical Engineering, University of California, Los Angeles, CA, 1996, pp. xi, 1-51.
Moreau de Saint-Martin, Francois et al., “Design of Optimal Linear-Phase Transmitter and Receiver Filters For Digital Systems,” IEEE, 1995, pp. 885-888.
Proakis, John G. et al., “Digital Signal Processing: Principles, Algorithms, and Applications,” Macmillian Publishing Company, New York, pp. 485-502, undated.
Samueli, Henry, “On the Design of Optimal Equiripple FIR Digital Filters for Data Transmission Applications,” IEEE Transactions on Circuits and Systems, vol. 35, No. 12, Dec. 1998, pp. 1542-1546.
Samueli, Henry, “On the Design of FIR Digital Data Transmission Filters with Arbitrary Magnitude Specifications,” IEEE Transactions on Circuits and Systems, vol. 38, No. 12, Dec. 1991, pp. 1563-1567.
Thompson, Charles D. et al., “A Digitally-Corrected 20b Delta-Sigma Modulator,” IEEE International Solid-State Circuits Conference, Session 11/Oversampled Data Conversion/Paper TP 11.5, IEEE 1994, pp. 194-195.
Vaidyanathan, P.P., “Mulirate Systems and Filter Banks,” Prentice Hall, Englewood Cliffs, NJ 07631, pp. 118-134, undated.
Kuskie C. et al. (1995) “A Decimation Filter Architecture for GHz Delta-Sigma Modulators,” IEEE Int'l Symposium on Circuits and Systems, pp. 953-956.
Nagari, A. et al., “A 2.7V 11.8 mW Baseband ADC with 72 db Dynamic Range for GSM,” 1999, IEEE, Custom Integrated Circuits Conference, pp. 133-136.

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