Bypass scheme for ROM IC

Details Bypass scheme for ROM IC Bypass scheme for ROM IC

1993-07-21

1995-01-31

LaRoche, Eugene R.

Static information storage and retrieval

Read only systems

365200, G11C 1700

Patent

active

053863801

ABSTRACT:
A ROM IC includes an extra bit line. The extra bit line outputs a first binary logic signal when a word line in a no-use area is attempted to be read and a second binary logic signal when a word line in a use area is attempted to be read. The output of the extra bit line overrides the normal output of the ROM when a word line in a no-use area is attempted to be read, so that the output of a read operation in the no-use area is always a predetermined binary value. This predetermined binary output value occurs in spite of the fact that because of a defect the actual logic value of a storage location in the word line to be read in the no-use area is other than a desired value. When a word line in the use area is read, the output of the extra bit line does not override the actual binary value stored in the word line. Using the extra bit line and associated override circuitry, a ROM IC with a few defects in a no-use area may still be used in an application. It should be noted that the addition of the extra bit line in the ROM does not significantly increase the amount of chip "real estate" occupied by the ROM.

REFERENCES:
patent: 5034925 (1991-07-01), Kato
patent: 5124948 (1992-06-01), Takizawa
patent: 5195057 (1993-03-01), Kasa

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