Bypass scan path and integrated circuit device using the same

Details Bypass scan path and integrated circuit device using the same Bypass scan path and integrated circuit device using the same

1997-05-23

1998-11-24

Beausoliel, Jr., Robert W.

Excavating

371 226, 371 225, G06F 1300

Patent

active

058417915

ABSTRACT:
A plurality of bypass scan paths are provided in series between an SI terminal and an SO terminal to constitute a scan path for propagating serial data. In each of bypass scan paths, a selection data propagation holding register and a mode data propagation holding register are not connected in series with a scan register as in a conventional scan path, but arranged on a bypass path formed by a bypass line. Therefore, the selection data propagation holding register and the mode propagation holding register carry out none of unnecessary shifting operation in a bypass scan path selecting a register path at the time of propagation of test data and test result data. As a result, a time period can be reduced for shifting in test data and shifting out test result data.

REFERENCES:
patent: 4872169 (1989-10-01), Whetsel, Jr.
patent: 5150044 (1992-09-01), Hashizume et al.
patent: 5260949 (1993-11-01), Hashizume et al.
Riessen et al., An Architecture w/ Boundary Scan, Feb. 1990, pp. 9-17.
"Designing and Implementing an Architecture with Boundary Scan", R.P. Van Riessen et al., IEEE Design & Test of Computers, Feb. 1990, pp. 9-19.
"Implementing Macro Test in Silicon Compiler Design", Frans Beenker et al., IEEE Design & Test of Computers, Apr. 1990, pp. 41-51.
"An Enhancement of Cell-Based Test Design Method for Boundary Scan Architecture", Takeshi Hashizume et al. Nov. 21, 1990, pp. 63-69.
"IEEE Standard Test Access Port and Boundary-Scan Architecture", May 21, 1990, Chapter 4 and 6.

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