Bypass scan path and integrated circuit device using the same

Details Bypass scan path and integrated circuit device using the same Bypass scan path and integrated circuit device using the same

1992-06-19

1995-09-05

Voeltz, Emanuel T.

Excavating

371 221, G01R 3128

Patent

active

054485754

ABSTRACT:
A bypass scan path is formed of a scan path and a scan path selecting circuit. The scan path has its operation controlled with a control signal group including a strobe signal, an update signal, shift clock signals. The scan path selecting circuit has its operation controlled with a reset signal and the control signal group for the scan path, and requires no other control signals. The reset signal and the control signal group for the scan path can be generated by a test controller defined in the standard of the boundary scan test of the IEEE 1149.1.

REFERENCES:
patent: 4860290 (1989-08-01), Daniels et al.
patent: 4872169 (1989-10-01), Whetzel, Jr.
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5130647 (1992-07-01), Sakashita et al.
patent: 5150044 (1992-09-01), Hashizume et al.
patent: 5260949 (1993-11-01), Hashizume et al.
Van Riessen et al. publication, IEEE Design & Test of Computers, Feb. 1990, pp. 9-19, "Designing and Implementing an Architecture with Boundary Scan".
Beenker publication, IEEE Design & Test of Computers, Apr. 1990, pp. 41-51, "Implementing Macro Test in Silicon Compiler Design".
Hashizume et al. publication in IEICE Technical Report, "An Enhancement of Cell-Based Test Design Method for Boundary Scan Architecture", Nov. 1990, pp. 63-69.

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