Bypass circuitry for use in a pipelined processor

Details Bypass circuitry for use in a pipelined processor Bypass circuitry for use in a pipelined processor

2006-08-15

2006-08-15

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

Reexamination Certificate

active

07093107

ABSTRACT:
There is disclosed a data processor that uses bypass circuitry to transfer result data from late pipeline stages to earlier pipeline stages in an efficient manner and with a minimum amount of wiring. The data processor comprises: 1) an instruction execution pipeline comprising a) a read stage; b) a write stage; and c) a first execution stage comprising E execution units that produce data results from data operands. The data processor also comprises: 2) a register file comprising a plurality of data registers, each of the data registers being read by the read stage of the instruction pipeline via at least one of R read ports of the register file and each of the data registers being written by the write stage of the instruction pipeline via at least one of W write ports of the register file; and 3) bypass circuitry for receiving data results from output channels of source devices in at least one of the write stage and the first execution stage, the bypass circuitry comprising a first plurality of bypass tristate line drivers having input channels coupled to first output channels of a first plurality of source devices and tristate output channels coupled to a first common read data channel in the read stage.

REFERENCES:
patent: 4591973 (1986-05-01), Ferris et al.
patent: 4982283 (1991-01-01), Acampora
patent: 5467476 (1995-11-01), Kawasaki
patent: 5764943 (1998-06-01), Wechsler
patent: 5805852 (1998-09-01), Nakanishi
patent: 5872986 (1999-02-01), Heeb
patent: 5974537 (1999-10-01), Mehra
patent: 6078196 (2000-06-01), Gayles
patent: 6105123 (2000-08-01), Raje
patent: 6167501 (2000-12-01), Barry et al.
patent: 6170051 (2001-01-01), Dowling
patent: 0 730 223 (1996-09-01), None
Patterson et al., Computer Organization & Design: The Hardware/Software Interface, 1998, Morgan Kaufmann Publishers, p. B-9.
Katz, Randy H. “Contemporary Logic Design”. University of California. Benjamin Cummings/Addison Wesley Publishing Company 1993. © 1996 Chapter 11: Computer Organization. Section 3: Busing Strategies. http://www2.ele.ufes.br/˜ailson/digital2/cld/CLD.ht.
Trainis. Simon A.; “Modelling the Hardware Cost of Full Register Bypassing in a Multiple Instruction Issue Processor”; XP 000679755;. Journal of Systems Architecture; 1997 Published by Elsevier Science B.V.; pp. 39-46.

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